Jetway 939GT4 user manual download (Page 62 of 64)

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Page 62 of 64
i7
Code(hex)
Name
Description
77
Display POST error
Check POST error and display them
and ask for user intervention
Ask password security (optional).
78
CMOS and Option
ROM Init
Write all CMOS values back to RAM and
clear screen.
Enable parity checker
Enable NMI, Enable cache before boot.
Initialize any option ROMs present
from C8000h to EFFFFh.
NOTE: When FSCAN option is enabled,
ROMs initialize from C8000h to
F7FFFh.
79
Reserved
7A
Reserved
7B
Reserved
7C
Reserved
7D
Boot Medium
detection
Read and store boot partition head and
cylinders values in RAM
7E
Final Init
Final init for last micro details
before boot
7F
Special KBC patch
Set system speed for boot
Setup NumLock status according to
Setup
80
Boot Attempt
Set low stack
Boot via INT 19h.
FF
Boot
S4 POST Codes
Code(hex)
Name
Description
5A
Early Chipset Init Early Initialized the super IO
Reset Video controller
Keyboard controller init
Test the Keyboard
Initilized the mouse
5B
Cmos Check
Check Cmos Circuitry and reset CMOS
5C
Chipset default
Prog
Program the chipset registers with
CMOS values. Init onboard clock
generator
5D
Identify the CPU
Check the CPU ID and init L1/L2 cache
5E
Setup Interrupt
Vector Table
Initialize first 120 interrupt
vectors with SPURIOUS_INT_HDLR and
INT 00h-1Fh according to INT_TBL
First step initialize if single CPU
Onboard. Re-init KB
If support HPM, HPM get initialized
Here.
5F
Test CMOS
Interface and
Battery status
Verifies CMOS is working correctly,
detects bad battery. If failed, load
CMOS defaults and load into chipset
60
KBC final Init
Final Initial KBC and setup BIOS data
area
Sample